Santa Clara, CA (PRWEB)
July 25, 2017
Blue Pearl Software, Inc., the leading provider of design automation software for ASIC, FPGA and IP RTL verification, today announced Visual Verification Suite 2017.2. The release extends Blue Pearl’s leadership in RTL verification of Xilinx® All Programmable FPGAs and SoCs with direct integration inside the Vivado® Design Suite accelerating setup, analysis and debug of FPGA IP and designs.
The Visual Verification Suite 2017.2 provides an advanced integrated RTL linting, constraint generation and clock domain crossing analysis and debug environment, so that designers can verify as they code. With the suite, RTL developers produce the highest level of quality code, in the least amount of time. It is proven to help avoid costly and time consuming design re-spins due to simulation vs. hardware mismatches, structural issues, invalid constraints and metastability issues.
The new release provides built in FPGA libraries, vendor specific rules such as the Xilinx UltraFast™Design Methodology, and now users can also download the Blue Pearl app from the Xilinx Tcl Store to integrate the Visual Verification Suite inside the Vivado interactive design environment for fast setup and verification. In addition, with the app, users can track key project metrics over time, such as power, area, and max frequency with Visual Verification Suite’s Management Dashboard.
“The Xilinx Tcl Store makes it easy to find and share Tcl scripts contributed by the development community and partners like Blue Pearl. With the power of Tcl, these scripts extend the core functionality of the Vivado Design Suite, further enhancing productivity and ease of use” said Greg Daughtry, Director of Product Marketing at Xilinx.
The 2017.2 release also features direct project import for Intel®/Altera Quartus® Prime Software and Microsemi®…